CARTRIDGE CONNECTORS
2.
Pin
—
Pin
Pin
Ä
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
a
43
45
47
49
Pin
T
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17-32
28
49
50
vo
Name
°
CSI
cs12
o
-
Reserve
WAIT
1
o
Mi
o
IORQ
WR
o
0
RESET
o
A9
o
A11
o
A7
o
A12
o
A14
o
Al
o
A3
o
A5
vo
Dt
vo
D3
vo
D5
D7
Vo
GND
=
-
GND
-
+5SV
-
+5V
SOUNDIN
1
Content
ROM
ROM
ROM
Slot
Reserved
Refresh cycle signal
CPU's
Interrupt
Signal expressing
This signal controls direction
Cartridges
cartridge at data transmission time
IORQ
V/O
Memory
MERG
Write timing
WR
Read timing
RD
RESET
System reset signal
Reserve
Reserved
-
A15
Address bus signals
A0
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
addresses
4000
7FFF
—
addresses
8000
—
addresses
4000
—BFFF
select signal
line
signal
use
—
WAIT
request signal
signal
request
CPU
fetch cycle
are
selected and
request signal
request signal
signal
signal
line
use
signal
1
2
Name
cS2
SLTSL
RFSH
INT
BUSDIR
MERG
RD
Reserve
A15
A10
A6
A8
A13
AO
A2
A4
DO
D2
D4
D6
CLOCK
Swi
sw2
+12V
—12V
si
select
BFFF
select signal
select
(for
signal
inhibited
to
CPU
external data bus buffer
of
is
output
from
L
level
inhibited
vo
o
o
o
l
1
o
o
-
o
o
o
o
o
o
o
o
vo
vo
vo
vo
o
-
-
-
-
256k
ROM)
each